ASIC/FPGA Implementation

imageODLINX is dedicated to helping its customers with ASIC and FPGA projects. Utilizing our expertise in designing state-of-the-art products we have successfully taken multiple ASIC and FPGA projects from definition to tapeout.
We have worked over the years on multiple projects in multiple markets:Wireless, Networking, Graphics and PC core-logic. However our core strength is in implementation of DSP functions for ASICs and FPGAs. We have implemented baseband processors, modems and DSP engines for wireless systems such as 802.11, UWB, Bluetooth and WCDMA. 
In our engagement with our clients we typically provide them with all the necessary engineering services to complete their project. Starting from a system specification document or high-level abstract model (such as a matlab or C/C++ model)  we would then take the project through all the necessary steps to provide our clients with a tested, robust and well documented system. We are experts in FPGA design flows (Altera and Xilinx) as well as ASIC design flows and very often complement these design flows with our own custom tailored CAD tools to further automate and augment the industry standard toolsets.

Intellectual Property Design Services

  • Complete turn-key solution to your challenging ASIC or FPGA product concept through our detail oriented Turn-Key Design Flow
  • DSP algorithm implementation (floating-point and fixed-point)
  • DSP core implementation such as: ECC cores, Arithmetic co-processors, Crypto cores, Digital (de)modulation cores
  • Wireless interface base-band-processor (BBP) implementation such as: 802.11, UWB, Bluetooth
  • High speed protocol-interface implementation such as: USB, PCIE, SATA, HDMI, IEEE-1394, Ethernet
  • Video codec implementation such as: H.264
  • SoC interconnect core implementation such as: AMBA, WISHBONE switches, arbitration, bridges.
  • Optimized computer arithmetic libraries
  • Customized micro-controllers
  • Guaranteed "clean" RTL code (Verilog HDL) through comprehensive LINT tool usage.
  • Low power design

SoC Services

  • Timing Constraint development
  • Formal Equivalence Checking, for guaranteed netlist consistency
  • Post layout bug fixes through Engineering Change Orders (ECO)
  • Multiple clock domain design
  • Logic synthesis and Static Timing Analysis

Backend Layout Services

Augmenting our own services with services from leading back-end service providers, we provide a complete RTL to GDSII to Foundry turn-key solution:
  • Floorplanning
  • Clock Tree Synthesis
  • Physical synthesis
  • Placement and Routing
  • Design closure
  • LVS/DRC
  • GDSII generation
  • ASIC foundry release processin
  

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